Design of a switch for network on chip applications

System on Chip (SOCJ design in theforthcoming billion transisror era will involve the integration of numerous hererogeneous semiconductor intellectual proper@ ( I f ) blocks. Some of the main problems in the ultra deep sub micron technologies characterized by gate lengths in rhe range of 50-100 nm arise from non-scalable global wire delays, failure ro achieve global synchronization, errors due to signal integritj issues, and difficulties associared with non-scalable bus-based functional interconnecr. These problems are addressed in rhis paper by inrroducing a new design methodology. A switch-based network-centric archirecture to inrerconnect If blocks is proposed. We introduce a ' butterfly fat wee architecture as an overall inrerconnect template. In this new interconnect archirecrure, switches are used ro transfer data between If blocks. To reduce overall latency and hardware overhead, wormhole routing is adopred. The proposed switch architecrure supports rhis routing method. Initial implemenrarion of the switch reveals rhot the total swirch area is expected to amount to less than 2% of a large SOC. KeywordsSysrem on chip, network on chip. switch, butterfly fat tree, wormhole routing, interconnect architecture.